Credits and Contact Hours
1 credit, 30 hours
Course Coordinator's Name Dr. Shouq Alsubaihi
Textbook
Laboratory notes and manual for QUARTUS CAD tool
Catalog Description
Hands-on design and implementation of digital logic circuits. Use of CAD tools for schematic capture and Verilog HDL based simulation and synthesis. Implementations of digital circuits using sophisticated logic devices such as CPLDs and FPGAs.
Co-requisite
CpE-262
Specific Goals for the Course
Upon successful completion of this course, students will be able to:
Implement the concepts learned in the digital logic course with CAD tools.
Become familiar with digital lab equipment, breadboards, wiring and logic chips.
Behave safely and ethically in a laboratory environment
Conduct experiment with logic circuits in SOP and POS form using logic gates. (Student outcomes: 6)
Conduct experiment by synthesizing, verifying and implementing combinational digital circuits (code converter, adder, logic unit) using QuartusII CAD tool. (Student outcomes: 6)
Conduct experiment by designing, simulating and implementing a counter and/or a shift register. (Student outcomes: 2, 6)
Conduct experiment by designing, simulating and implementing a Moore type FSM. (Student outcomes: 2, 6)
Conduct experiment by prototyping logic designs using CPLDs and FPGAs. (Student outcomes: 2)
Complete a design project and document their work in a technical report. (Student outcomes: 2, 3)
Topics to Be Covered
Introduction to digital lab equipment, safety rules and Altera DE2-115 Board
Introduction to Altera Quartus-II computer-aided design tool
Synthesis of logic circuits in SOP and POS form
Design, test, and implementation of a standard combinational circuit (code converter, ROM) using Verilog HDL in Quartus-II environment
Design, test, and implementation of an n-bit adder circuit using schematic and/or Verilog HDL
Design, simulation, and implementation of logic circuit using multiplexers
Analysis of sequential logic elements, and their behavior and use
Design, simulation, and implementation of a parallel load shift register
Design, simulation and implementation of a Moore type FSM using Quartus-II