Computer Architecture Laboratory

CPE

469

Hands-on design and implementation of computer system design. Use of CAD tools for schematic capture and Verilog HDL based simulation and synthesis. Design and implementation of data path functional units and I/O subsystem of traditional computer systems using sophisticated logic devices such as CPLDs and FPGAs.

Corequisites:

0612468

0612469

(0-3-1)

Credits and Contact Hours

1 credit, 30 hours

Course Instructor Name

Prof. Imtiaz Ahmad, Dr. Mohammad Al-Failakawi

Textbook

Laboratory notes and manual for QuartusII CAD tool.

Rabid Prototyping of Digital Systems: A Tutorial Approach, J. Hamblen and M. Furman.

Computer Organization and Design RISC-V Edition: The Hardware Software Interface,1st Edition, David Patterson and John Hennessy, Morgan Kaufmann. ISBN: 978-0-12-812275-4, 2018.

David Kirk and Wen-mei Hwu, Programming Massively Parallel Processors: A Hands-on Approach, 3rd Edition, ISBN: 9780128119860, Morgan Kaufmann, 2017.

Catalog Description

Hands-on design and implementation of computer system design using sophisticated logic devices such as FPGAs. Use of CAD tools for schematic capture and Verilog HDL based simulation and synthesis of data path functional units of traditional computer systems. Introduce students to writing parallel programs for multicore or GPUs.

Co-requisite

CpE-468

Specific Goals for the Course

Upon successful completion of this course, students will be able to:

Implement the concepts learned in the computer organization and computer architecture courses with CAD tools.

Behave safely and ethically in a laboratory environment.

Conduct experiment by synthesizing, verifying and implementing computer main functional units (register file, ALU) using QuartusII CAD tool. (Student outcomes: 2, 6)

Conduct experiment by designing, simulating and implementing a pipelined processor. (Student outcomes: 6)

Conduct experiment by prototyping a pipelined processor using CPLDs and FPGAs. (Student outcomes: 2, 6)

Practice teamwork to complete a design project and document their work in a technical report. (Student outcomes: 3)

Conduct experiment on parallel programming in CUDA C using GPU. (Student outcomes: 6)

Topics to Be Covered

Building the RISC-V Single Cycle Datapath

Extending the Single Cycle RISC-V Datapath to support a new instruction -- Testing and Simulation

Partitioning the RISC-V datapath into five pipeline stages

Resolving data hazards with forwarding and stall

Design, simulation, and implementation of parallel programming in CUDA C using GPU (CUDA API, CUDA memory model, shared memory) lab 1

CUDA Programming lab 2

CUDA Programming lab 3