Design of GNRFET Based-Mixed Logic Decoders For Low-Power Applications (Prof. Mahmoud Ben Naser)

GNRFETs are an alternative solution to the scaling challenges that MOSFET devices face at 22nm and beyond. These GNRFETs offer superior performance while significantly reducing power consumption due to their unique structure and excellent electrical properties. In this thesis, we introduce four distinctive designs for 2-4 Mixed Logic Decoders (MLDs) and four more designs for 4-16 Mixed Logic Decoders (MLDs). All these designs are implemented using 22nm GNEFET and 22nm MOSFET. Using Synopsys HSPICE tool, 2-4 and 4-16 MLDs are simulated and analyzed in terms of total average power, delay, and power-delay product (PDP). Compared to MOSFET designs, the simulation results of 2-4 GNRFET based-MLDs show power enhancements of 95.69% to 98.02% and PDP improvements of 85.23% to 95.14%. As for 4-16 MLDs, the GNRFET results demonstrate outstanding improvements in total average power consumption and PDP by approximately 99%, proving that the improvement increases as the circuit expands. In this thesis, we also present four novel and innovative designs for 2-4 Mixed Logic Decoders that combine GNRFET technology with a circuit-level power gating technique called Gated VDD to maximize power saving. Our creative designs achieve impressive improvements in total average power consumption by 96.57% to 99.01% and in PDP by 87.97% to 97.67%, emphasizing the significant potential of using GNRFET with a Gated VDD technique in optimizing power consumption and power-delay product.

Supervisor: Prof. Mahmoud Ben Naser
Convener: Prof. Mehmet Karaata
Examination Committee: Prof. Mehmet Karaata , Prof. Abbas Fairouz