Enhanced Constant Multiplier and Approximate Logarithmic Multiplier Implementation using POSIT format based on FPGA (Dr. Sa'ed Abed)

In hardware design, the high performance, power efficiency, and reconfigurable nature of FPGAs are becoming increasingly desirable. Constant multiplication can consume significant hardware and consequently increase power consumption. To address these issues, we propose the enhanced constant multiplier (ECM), a novel multiplier implemented using the POSIT format. The ECM utilizes only four DSP units, efficiently multiplying and adding partial products within each DSP unit. Compared to traditional POSIT CMs, the ECM demonstrates substantial improvements: a 32% reduction in area, a 34% reduction in delay, a 28% reduction in power consumption, and a 53% reduction in energy, all without sacrificing accuracy.
In addition to the ECM, another multiplier is implemented in the POSIT format which is the approximate logarithmic multiplier (ALM). The ALM generally goes through three steps: binary-to-logarithm, addition, and logarithm-to-binary. These steps are power-intensive, representing the primary drawback of the ALM. To mitigate this, we introduce the enhanced approximate logarithmic multiplier (EALM), a novel multiplier also in the POSIT format. The EALM employs a custom adder based on the propagate and generate concept to add the lower 8 bits, while the remaining bits are summed using a traditional “+” operation. Compared to the traditional POSIT ALMs, the EALM reduces area, power usage, energy consumption by 16%, 26%, and 20% respectively, with an 8.69% increase in delay. 

Supervisor: Dr. Sa'ed Abed
Convener: Prof. Imtiaz Ahmad
Examination Committee: Dr. Mohammad Alfailakawi